Biography

Since June 2019 I’m a Research Scientist at Stanford University in the Centaur lab. From 2017 to 2019 I was a postdoctoral researcher in the same lab. I received my PhD in computer science from Johannes Kepler University Linz (Austria), supervised by Armin Biere within the National Research Network (NFN) on Rigorous Systems Engineering (RiSE).

My main area of research is in Satisfiability Modulo Theories (SMT) with a particular interest in developing solvers for (quantified) bit-vectors, and arrays. I’m also interested in automated testing and debugging techniques to develop tools that help developers to test their SMT solvers.

SMT Solvers

I’m one of the main developers of the SMT solver Boolector (since June 2012) and Bitwuzla. Since June 2017 I’m also part of the developer team and one of the senior technical leads of the SMT solvers CVC4 and its successor cvc5.

Education

• Doctor of Technical Sciences (Dr.techn.) in Computer Science, 2017
  Johannes Kepler University, Linz, Austria
• MSc (Dipl.-Ing.) in Computer Science, 2012
  Johannes Kepler University, Linz, Austria
• BSc in Computer Science, 2010
  Johannes Kepler University, Linz, Austria

Academic Service

Since 2017 I’m one of the maintainers of the SMT-LIB benchmarks.

2025

• FMCAD 2025 (PC member)
• POS 2025 (PC member)
• SMT 2025 (PC member)

2024

• HWMCC 2024 (Co-organizer)
• FMCAD 2024 (PC member)
• ATVA AE 2024 (Co-chair)
• CAV 2024 (PC member)
• AEiC 2024 (PC member)

2023

• SMT 2023 (Program co-chair)
• SMT Steering Committee (ex-offizio member as SMT Workshop rep.)
• SBMF 2023 (PC member)
• FMCAD 2023 Student Forum (PC member)

2022

• FMCAD 2022 Student Forum (Chair)
• SMT 2022 (PC member)
• TACAS 2022 (AEC member)

2021

• ATVA 2021 (PC member)
• SMT 2021 (PC member)
• CAV 2021 (AEC member)

2020

• HWMCC 2020 (Co-organizer)
• LogicLounge 2020 (summer) (Co-organizer)
• SMT 2020 (PC member)

2019

• HWMCC 2019 (Co-organizer)
• CAV 2019 (AEC member)
• SMT 2019 (PC member)

2018

• QBF 2018 (PC member)