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RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture
that utilizes a small, highly-optimized set of instructions, rather than a more specialized
set of instructions often found in other types of architectures.
History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early
80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar
philosophy which has become known as RISC. Certain design features have been characteristic of
most RISC processors:
- one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle.
This is due to the optimization of each instruction on the CPU and a technique called ;
- pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions
to more efficiently process instructions;
- large number of registers: the RISC design philosophy generally incorporates a larger number
of registers to prevent in large amounts of interactions with memory
This Site
We will first examine MIPS in detail as an example of an early RISC architecture
to better understand the features and design of RISC architectures. We will then study pipelining
to see the performance benefits of such a technique. Then we will look at the advantages and disadvantages of such a RISC-based
architecture as compared to CISC architectures. Finally, we will discuss some of the recent developments and future directions
of RISC processor technology in particular, and processor technology as a whole in general.
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