Stanford EE CS Colloquium: Petascale Deep Learning on a Single Chip, Tapabrata Ghosh , Vathys

Stanford EE CS Colloquium

Title: Petascale Deep Learning on a Single Chip
Speaker: Tapabrata Ghosh , Vathys
Date: December 6, 2017
Time: 4:30pm
Location: NEC Auditorium, Gates Computer Science Building Room B3

Abstract: is a deep learning startup that has been developing a newdeep learning processor architecture with the goal of massively improvedenergy efficiency and performance. The architecture is also designed tobe highly scalable, amenable to next generation DL models. Although deeplearning processors appear to be the "hot topic" of the day in computerarchitecture, the majority (we argue all) of such designs incorrectlyidentify the bottleneck as computation and thus neglect the true culpritsin inefficiency; data movement and miscellaneous control flow processoroverheads. This talk will cover many of the architectural strategiesthat the Vathys processor uses to reduce data movement and improveefficiency. The talk will also cover some circuit level innovationsand will include a quantitative and qualitative comparison to many DLprocessor designs, including the Google TPU, demonstrating numericalevidence for massive improvements compared to the TPU and other suchprocessors.

Tapabrata ("Tapa") Ghosh is the co-founder and CEO of where hedevelops the core architecture of the Vathys deep learning processor. Whenhe was a teenager, he developed a quadcopter drone with the intentionof utilizing deep learning to make collision free drones, at the timea novel proposition. In attempting to do so, he experienced firsthandthe computational requirements of deep learning in the real world. Theexperience led him to found Vathys with the goal of developing performantand power efficient deep learning processors. He also has multiple patentsand papers related to the fields of deep learning, computer architectureand semiconductors.

Wednesday, December 6, 2017 - 4:30pm to 5:30pm
NEC Auditorium, Gates Computer Science Building Room B3