CISC and RISC Convergence
State of the art processor technology has changed significantly since RISC chips were first introduced in the early '80s. Because a number of advancements (including the ones described on this page) are used by both RISC and CISC processors, the lines between the two architectures have begun to blur.
In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining. With other technological improvements, it is now possible to fit many more transistors on a single chip. This gives RISC processors enough space to incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated hardware, making use of extra function units for superscalar execution. All of these factors have led some groups to argue that we are now in a "post-RISC" era, in which the two styles have become so similar that distinguishing between them is no longer relevant.
However, it should be noted that RISC chips still retain some important traits. RISC chips stricly utilize uniform, single-cycle instructions. They also retain the register-to-register, load/store architecture. And despite their extended instruction sets, RISC chips still have a large number of general purpose registers.
Simultaneous Multi-Threading (SMT) allows multiple threads to be executed
at the exact same time. Threads are series of tasks which are executed
alternately by the processor.
Normal thread execution requires threads to be switched on and off the processor
as a single processor dominates the processor for a moment of time. This allows
some tasks that involve waiting (for disk accesses, or network usage) to execute more
SMT allows threads to execute at the same time by pulling instructions
into the pipeline from different threads. This way, multiple threads
advance in their processes and no one thread dominates the processor
at any given time.
Value prediction is the prediction of the value that a particular load instruction will produce. Load values are generally not random, and approximately half of the load instructions in a program will fetch the same value as they did in a previous execution. Thus, predicting that the load value will be the same as it was last time speeds up the processor since it allows the computer to continue without having to wait for the load memory access. As loads tend to be one of the slowest and most frequently executed instructions, this improvement makes a significant difference in processor speed.